Differences between Memory Mapped I/O and DMA mode of data transfer

MEMORY MAPPED I/O

Memory-mapped I/O uses the same address space to address both memory and I/O devices. The memory and registers of the I/O devices are mapped to (associate with) address values. So when an address is accessed by the CPU, it may refer to a portion of physical RAM, or it can instead refer to memory of the I/O device. Thus, the CPU instructions used to access the memory can also be used for accessing devices. Each I/O device monitors the CPU’s address bus and responds to any CPU access of an address assigned to that device, connecting the data bus to the desired device’s hardware register. To accommodate the I/O devices, areas of the addresses used by the CPU must be reserved for I/O and must not be available for normal physical memory.

Memory-mapped I/O uses the same address bus to address both memory and I/O devices, and the CPU instructions used are same for accessing the memory and also accessing devices. Memory mapping can also improve performance by lowering memory requirements. It uses one less buffer to store the data i.e. a single buffer is shared between the kernel space and user space.

Features of Memory Mapped I/O

· I/O devices are mapped into memory space.

· I/O devices are allotted memory addresses.

· Processor does not differentiate between memory and I/O. Treats I/O devices also like memory devices.

· I/O addresses are as big as memory addresses. E.g.:: in 8085, I/O addresses will be 16 bit as memory addresses are also 16-bit.

· This allows us to increase the number of I/O devices. E.g.:: in 8085, we can access up to 216 = 65536 I/O devices.

· We can transfer data from I/O devices using any instruction like MOV etc.

· Data can be transferred using any register of the processor.

· We need only two control signals in the system: Read and Write.

· Memory addresses are big so address decoding will be slower.

· Address decoding will be more complex and costly.

DMA (DIRECT MEMORY ACCESS)

The data transfer between a fast storage media such as magnetic disk and memory unit is limited by the speed of the CPU. Thus we can allow the peripherals directly communicate with each other using the memory buses, removing the intervention of the CPU. This type of data transfer technique is known as DMA or direct memory access. During DMA the CPU is idle and it has no control over the memory buses. The DMA controller takes over the buses to manage the transfer directly between the I/O devices and the memory unit. To Perform a DMA transfer we need a DMA Controller like 8237/ 8257.

Mechanism of DMA

1. By Default Processor is the bus master.

2. The DMA transfer parameters first initialized by the processor.

3. Processor programs two registers inside the DMAC called CAR and CWCR giving the starting address and the number of bytes to be transferred.

4. DMAC now ensures that the I/O device is ready for the transfer by checking the DREQ signal.

5. If DREQ=1, then DMAC gives HOLD signal to the Processor requesting control of the system bus.

6. Processor releases control of the bus after finishing the current machine (bus) cycle.

7. Processor gives HLDA informing DMAC that it is now the bus master.

8. DMAC issues DACK (by default active low, but can be changed) to I/O device indicating that the transfer is about to begin.

9. Now DMAC transfers one byte in one cycle.

10. After every byte is transferred the Address register and Count register are decremented by 1.

11. This repeats till Count reaches “0” also called Terminal Count.

12. Now the transfer is complete.

13. DMAC returns the system bus to Processor by making HOLD = 0

14. Processor once again becomes bus master

Advantage of DMA

DMA transfers are very fast.

Drawback of DMA

DMAC becomes the bus master. Hence during DMA cycles, the processor cannot perform any operations as the bus is already being used for DMA. The processor remains in HOLD state.

Types of DMA transfer

· Block transfer mode / Burst mode: In this mode, the DMAC is programmed to transfer ALL THE BYTES in one complete DMA operation. After a byte is transferred, the CAR and CWCR are adjusted accordingly. The system bus is returned to the processor, ONLY after all the bytes are transferred. It is the fastest form of DMA but keeps the processor inactive for a long time.

· Single byte transfer mode / Cycle stealing: Once the DMAC becomes the bus master, it will transfer only ONE BYTE and return the bus to the processor. As soon as the processor performs one bus cycle, DMAC will once again take the bus back from the processor. Hence both DMAC and processor are constantly stealing bus cycles from each other. It is the most popular method of DMA, because it keeps the processor active in the background. After a byte is transferred, the CAR and CWCR are adjusted accordingly.

· Demand transfer mode: It is very similar to Block Transfer, except that the DREQ must remain active throughout the DMA operation. If during the operation DREQ goes low, the DMA operation is stopped and the busses are returned to the processor. In the meantime, the processor can continue with its own operations. Once DREQ goes high again, the DMA operation continues from where it had stopped. This means, the transfer happens on demand from the I/O device.

· Hidden mode / Transparent mode: In this mode, once the processor programs all parameters inside the DMAC, the DMAC does not request the processor for the control of the bus. Instead it observes the processor. It waits for the processor to enter idle state. Once the processor is idle, the DMAC will take control of the bus and perform the Transfer. So the Transfer is totally transparent to the processor or hidden from the processor.

DIFFERENCE